1. Field of the Invention
The present invention relates to an output buffer apparatus capable of adjusting the output impedance thereof.
2. Description of the Related Art
In a computer system, as the speed of a central processing unit (CPU) has increased, the propagation speed of signals between semiconductor devices and the propagation speed of signals between printed circuit boards have also increased. Note that microstrip lines or coaxial cables are used as transmission lines for transmitting high frequency signals.
When the frequency of transmitted signals is low, the wavelength of the transmitted signals is relatively large with respect to the length of the transmission line, so that the phases of the transmitted signals are approximately the same within the transmission line. Therefore, even when reflection noise is generated at a terminal of the transmission line due to a discrepancy between the output impedance of an output buffer apparatus and the characteristic impedance of the transmission line, since the phase of the reflection noise is the same as those of the transmitted signals, the transmitted signals are hardly distorted.
On the other hand, when the frequency of transmitted signals is high, the wavelength of the transmitted signals is relatively small with respect to the length of the transmission line, so that the phases of the transmitted signals are different from each other within the transmission line. Therefore, when reflection noise is generated at the terminal of the transmission line due to a discrepancy between the output impedance of the output buffer apparatus and the characteristic impedance of the transmission line, since the reflection noise may affect the transmitted signals, the transmitted signals are remarkably distorted.
In order to suppress the above-mentioned reflection noise, a terminal processing is carried out so that the characteristic impedance of the transmission line is brought close to an impedance at a signal transmitter side terminal, i.e., an output buffer of a first device or an impedance at a signal receiver side terminal, i.e., an input buffer of a second device which is connected via a transmission line to the first device.
Note that the terminal processing is divided into a parallel terminal processing where a resistance corresponding to the characteristic impedance is connected between the signal receiver terminal (the input buffer) and a power supply terminal (or the ground terminal) and a serial terminal processing where the output impedance of the signal transmitter side terminal (the output buffer) is brought close to the characteristic impedance of the transmission line.
In the above-mentioned serial terminal processing, a semiconductor chip including the output buffer is subject to environmental temperature, power supply voltage, manufacturing process and the like, so that the output impedance of the output buffer per se is subject to the environmental temperature, the power supply voltage, the manufacturing process and the like. Therefore, a prior art output buffer apparatus has been known to include an impedance adjusting circuit (see: JP-A-2002-94366). The output buffer apparatus is constructed by a main-buffer circuit including a plurality of P-channel MOS transistors each connected between a power supply terminal and an output terminal and a plurality of N-channel MOS transistors each connected between the ground terminal and the output terminal and a pre-buffer circuit including a plurality of first pre-drivers each driving one of the P-channel MOS transistors in accordance with a pull-up impedance adjusting signal and a data signal and a plurality of second pre-drivers each driving one of the N-channel MOS transistors in accordance with a pull-down impedance adjusting signal and the data signal. This will be explained later in detail.
In the above-described prior art output buffer apparatus, however, since the impedance adjusting signals are supplied to the pre-buffer circuit in asynchronization with the data signal, the output signal at the output terminal may be changed in the middle of data “1” or “0”, i.e., the output signal at the output terminal is distorted, thus deteriorating the quality thereof.